1. Field of the Invention
The various embodiments described herein relate to the field of multiprocessor computer systems and particularly to such systems including cryptographic processing units (i.e., crypto units), which are co-processor units dedicated for encrypting data after and decrypting data before processing by one of multiple processors.
2. Description and Disadvantages of the Prior Art
A typical example of the aforementioned multiprocessor computer systems is disclosed in IBM Journal of Research and Development, Volume 48, No. 3/4, May/July, 2004, pages 295-309. On page 299 thereof, an overview diagram of a prior art IBM eServer z990 processor is provided.
FIG. 1A illustrates an overview of the most basic structural components of such prior art multiprocessor computer system.
In this prior art cryptographic co-processor technology, each microprocessor core 12 includes a crypto unit 14 that implements clear key cryptographic engines in order to efficiently execute the most frequently-used cryptographic functions.
Generally, in this particular prior art, a cryptographic processing unit (i.e., crypto unit) comprises a cipher engine and a hash engine.
With increasing enhancements of processor performance, increasing numbers of cooperating processor cores, and steadily increasing cryptographic functionality as is demanded by steadily increasing cryptographic needs during instruction processing, an increasing amount of chip area and static power is required in order to provide such cryptographic functions on a processor chip according to the prior art, since in the prior art a crypto unit is required for each processor core. This 1:1 crypto unit to processor core relationship is required in order to manage the tight cooperation between a respective processor core 12 and a corresponding crypto unit 14, particularly in order to manage profound errors.
However, it is desired to keep the chip area consumption and the static power consumption of a multiprocessor system within some tolerable range, even with an increasing number of processor cores present in a single multiprocessor chip system.